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HD74HC160/HD74HC161/HD74HC162/ HD74HC163
Synchronous Decade Counter (Direct Clear) Synchronous 4-bit Binary Counter (Direct Clear) Synchronous Decade Counter (Synchronous Clear) Synchronous 4-bit Binary Counter (Synchronous Clear)
REJ03D0579-0200 (Previous ADE-205-455) Rev.2.00 Oct 11, 2005
Description
The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock input waveform. These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to the rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive edge of clock the count operation will be unaffected. All of these counters may be cleared by the utilizing clear input. The clear function on the HD74HC162 and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive edge of clock while the clear input is held low. The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the counter is cleared immediately regardless of the clock. Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high level portion of the QA outputs. The Ripple Carry output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
Features
* * * * * High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C)
Rev.2.00, Oct 11, 2005 page 1 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163 * Ordering Information
Part Name HD74HC160P HD74HC161P HD74HC162P HD74HC163P HD74HC160FPEL HD74HC161FPEL HD74HC162FPEL HD74HC163FPEL HD74HC160RPEL HD74HC162RPEL HD74HC163RPEL HD74HC161TELL Package Type Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation Taping Abbreviation (Quantity)
DILP-16 pin
P
--
SOP-16 pin (JEITA)
PRSP0016DH-B (FP-16DAV)
FP
EL (2,000 pcs/reel)
SOP-16 pin (JEDEC)
PRSP0016DG-A (FP-16DNV) PTSP0016JB-A (TTP-16DAV)
RP
EL (2,500 pcs/reel)
TSSOP-16 pin
T
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs Clear* Load Enable P L X X H L X H H H H H L H H X H : High level L : Low level X : Irrelevant Note: 1. 162 and 163 Only-160 and 161 are Asynchronous Clear Devices Decade Counter Clock
1
Outputs Enable T X X H X L Qn Reset-clear Load input data Count No count No count
Binary Counter HD74HC161 HD74HC163
Asynchronous clear Synchronous clear
HD74HC160 HD74HC162
Pin Arrangement
Clear 1 Clock 2 A3 B4 Data Inputs C 5 D6 Enable P 7 GND 8 (Top view) CK A B C D P CLR Ripple Carry QA QB QC QD Load T
16 VCC Ripple 15 Carry Output 14 QA 13 QB Outputs 12 QC 11 QD 10 Enable T 9 Load
Rev.2.00, Oct 11, 2005 page 2 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163
Logic Diagram
HD74HC160 Decade Counter with Asynchronous Clear
T1 CLR C C Load Load P1 T2 CLR C C Load Load P2 T3 CLR C C Load Load P3 T4 CLR C C Load Load P4 VCC CLR C C Load Load QA QA
QA
A
QB QB
QB
B
QC QC
QC
C
QD
QD
D
QD
Enable P Enable T Clear
Ripple Carry Output
Clock Load
Rev.2.00, Oct 11, 2005 page 3 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163 HD74HC161 4-bit Binary Counter with Asynchronous Clear
A
T1 CLR C C Load Load P1 T2 CLR C C Load Load P2 T3 CLR C C Load Load P3 T4 CLR C C Load Load P4
QA QA
QA
QB QB
QB
B
QC QC
QC
C
QD QD
QD
D
Enable P Enable T Clear CLR C C Load Load
Ripple Carry Output
Clock Load
Rev.2.00, Oct 11, 2005 page 4 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163 HD74HC162 Decade Counter with Synchronous Clear
T Q CK CK LD LD LD*CLR LD*CLR CLR CLR Q IN T Q CK CK LD LD LD*CLR LD*CLR CLR CLR Q IN T Q CK CK LD LD LD*CLR LD*CLR CLR CLR Q IN T Q CK CK LD LD LD*CLR LD*CLR CLR CLR Q IN
QA
A
QB
B
QC
C
QD
D P T CK VCC
RCO
CK CK
LD
LD LD LD*CLR LD*CLR CLR
CLR
CLR
Rev.2.00, Oct 11, 2005 page 5 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163 HD74HC163 4-bit Binary Counter with Synchronous Clear
T Q CK CK LD LD LD*CLR LD*CLR CLR CLR Q IN T Q CK CK LD LD LD*CLR LD*CLR CLR CLR Q IN T Q CK CK LD LD LD*CLR LD*CLR CLR CLR Q IN T Q CR CR LD LD LD*CLR LD*CLR CLR CLR Q IN
QA
A
QB
B
QC
C
QD
D P T CK
RCO
CK CK
LD
LD LD LD*CLR LD*CLR CLR
CLR
CLR
Rev.2.00, Oct 11, 2005 page 6 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163
Timing Diagram
HD74HC160/HD74HC162 Sequence illustrated in waveforms. 1. 2. 3. 4. Clear outputs to zero. Preset to BCD seven. Count to eight, nine, zero, one, two and three. Inhibit
Clear(HC160) Clear(HC162) Load A Data Inputs B C D Clock(HC160) Clock(HC162) Count Enables Enable P Enable T QA Outputs QB QC QD Ripple Carry Output (Asynchronous) (Synchronous)
7 Clear Load
8
9
0
1
2
3 Inhibit
Count
Rev.2.00, Oct 11, 2005 page 7 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163 HD74HC161/HD74HC163 Sequence illustrated in waveforms. 1. 2. 3. 4. Clear outputs to zero. Preset to binary twelve. Count to thirteen, fourteen, fifteen, zero, one and two. Inhibit
Clear(HC161) Clear(HC163) Load A Data Inputs B C D Clock(HC161) Clock(HC163) Count Enables Enable P Enable T QA Outputs QB QC QD Ripple Carry Output (Asynchronous) (Synchronous)
12 13 14 Clear Load
15
0
1
2 Inhibit
Count
Rev.2.00, Oct 11, 2005 page 8 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163
Absolute Maximum Ratings
Item Supply voltage range Input voltage Output voltage Output current DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT IOUT ICC, IGND IIK IOK PT Tstg Rating -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 25 50 20 20 500 -65 to +150 Unit V V V mA mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400
Unit V V C ns
Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25C Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 VIL 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL 2.0 4.5 6.0 4.5 Input current Quiescent supply current Iin ICC 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V IOH = -4 mA IOH = -5.2 mA Vin = VIH or VIL IOL = 20 A V Unit V Test Conditions
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.2.00, Oct 11, 2005 page 9 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Setup time tsu 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 Hold time th 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125 25 21 125 25 21 125 25 21 0 0 0 100 20 17 80 16 14 -- -- -- -- Typ -- -- -- -- 18 -- -- 23 -- -- 15 -- -- 16 -- -- 9 -- -- 15 -- -- -- -- -- -7 -- -- 7 -- -- 6 -- -- 5 -- 5 Max 5 25 29 160 32 27 225 45 38 150 30 26 200 40 34 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 156 31 26 156 31 26 156 31 26 0 0 0 125 25 21 100 20 17 -- -- -- -- Max 4 20 23 200 40 34 280 56 48 190 38 33 250 50 43 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 ns Clear to Clock (HC162, HC163 only) Unit MHz Test Conditions
tPLH, tPHL
ns
Clock to Q
ns
Clear to Q (HC160, HC161 only) Enable T to Ripple Carry output Clock to Ripple carry output
ns
ns
ns
Data to Clock
ns
Load to Clock
ns
Removal time
trem
ns
Pulse width
tw
ns
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Cin
pF
Rev.2.00, Oct 11, 2005 page 10 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163
Function Table
Count Enable/Disable
Control Inputs Load H L X X X H : High level Enable P Enable T H H H H L H H L L L L : Low level X : Irrelevant QA to QD Count No count No count No count No count Result at Outputs Ripple Carry Output High when QA to QD are maximum High when QA to QD are maximum L L
Test Circuit
Measurement point
CL*
Note: CL includes the probe and fig capacitance.
Rev.2.00, Oct 11, 2005 page 11 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163 Waveforms
1.
tW(H) Clock 50% tPHL QA, QB, QC, QD 50% Clock tPHL QA, QB, QC, QD 50% tPLH tW(L)
2.
Clear or Load tW 50% trem 50%
3.
Enable T 50% tPLH Ripple Carry Output 50% tPHL
4.
Clock 50% tPLH Ripple Carry Output 50% tPHL
5.
50% Clock tsu th tsu th 50%
50% Data
50%
50%
Rev.2.00, Oct 11, 2005 page 12 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
1
L
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-3.95x9.9-1.27
RENESAS Code PRSP0016DG-A
Previous Code FP-16DNV
MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.2.00, Oct 11, 2005 page 13 of 14
HD74HC160, HD74HC161, HD74HC162, HD74HC163
JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
JEITA Package Code P-TSSOP16-4.4x5-0.65
RENESAS Code PTSP0016JB-A
Previous Code TTP-16DAV
MASS[Typ.] 0.05g
*1
D F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
16
9
bp
*2
HE
E
c
Reference Symbol
Dimension in Millimeters Min Nom 5.0 4.40 Max 5.3
Index mark
Terminal cross section ( Ni/Pd/Au plating )
D E A2 A1 0.03
0.07
0.10 1.10
1 Z e
*3
8 bp L1 x M
A bp b1 c c
1
0.15
0.20
0.25
0.10
0.15
0.20
A
HE
0 6.20 6.40 0.65
8 6.60
A1
L
e x y
0.13 0.10 0.65 0.4
1
y
Detail F
Z L L 0.5 1.0
0.6
Rev.2.00, Oct 11, 2005 page 14 of 14
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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